Modern servers rely on multiple central processing units (CPUs) to meet the need for volume data processing and performance enhancement. Regardless how many processing units are adopted in a server, under current architecture, these processing units are distributedly disposed on the motherboard and connected through circuit layouts. Such architecture is problematic. First of all, each of the processing unit has numbers of pins connecting to the motherboard, and timing synchronization among these processing units is also a concern. Additionally, each of the processing units occupies a certain space of the motherboard. With the number of processing units adopted in the server increases, the size of the motherboard must be expanded as well. Those issues complicate the server's architecture design.
One of the conventional ways to solve the above issues is to package ICs, chips and/or dies in stacks. These methods are not without problem and the following are some examples.
The Chinese Pat. No. 101107710 describes a package for ICs with different sizes and functions stacked on a substrate. The size of the upper IC is larger than the size of the lower one, and the ICs are connected to the same substrate. The invention there describes that the resins must be prevented from flowing into the opening in the middle of the substrate, so that the light can pass through the opening. Similarly, the US Pat. Appl. No. US20060016973 also discloses a package where ICs with different sizes are connected to the same substrate and packaged; the middle of the substrate is opened for traversing light. Unlike the previous two, the opening portion taught in U.S. Pat. No. 8,531,019 is to dissipate the heat because its inwall is filled with metal wires and connected to a metal substrate and solder balls. In the U.S. Pat. No. 6,365,963, the package is provided for multiple ICs with various size and the opening is provided for connections. As for Taiwan Pat. No. TW200810063, the substrate is not made of glass, and the substrates therein are combined rather than separately connected to the packaging body. As evident from its FIG. 5(a), the structure may cause connection issues.
Apart from the aforementioned problems, these prior arts do not take into account the design of circuit layout. Given the drawbacks, the investor(s) of the present invention purpose a semiconductor device which not only resolves the circuit layout concern, but also increase the capacity of heat dissipation as well as decrease the overall packaging dimension.